Presently, there is a great demand for shrinking semiconductor devices to provide an increased density of devices on the semiconductor chip that are faster and consume less power. The scaling of devices in the lateral dimension requires vertical scaling as well so as to achieve adequate device performance. This vertical scaling requires the effective electrical thickness of the gate dielectric to be reduced so as to provide the required device performance.
Silicon dioxide has been the preferred gate dielectric material. However, newer technologies are requiring effective thicknesses of the silicon dioxide below currently believed limits (e.g., &lt;10 Angstroms). Therefore, there is interest in using higher dielectric constant (high-K) materials such as tantalum pentoxide and barium-strontium-titanate. Using a higher-K material allows for a greater physical thickness while obtaining a lower effective electrical thickness.
Unfortunately, most of the high-K materials being considered contain oxygen and/or are formed in an oxygen ambient. Therefore, during formation, silicon dioxide is formed on the surface of the substrate between the high-K dielectric and the substrate. The thickness of the silicon dioxide is such that much of the advantage to be obtained with the high-K material is lost.
In addition to silicon dioxide that can be formed during dielectric formation, the formation of polycrystalline silicon as a gate material on the high-K dielectric can also result in the formation of silicon dioxide. This has led to the use of metal gates on high-K dielectric material.
The threshold voltage of CMOS transistors is a critical parameter for the proper functioning of circuits made up of these devices. Among other factors, the threshold voltage is determined by the work function of the gate material and the semiconductor substrate. In using metal gates, the work function of the metal used is such that additional processing steps are required to obtain the correct threshold voltage. This additional processing can degrade the CMOS transistor performance. It is therefore desirable to use polycrystalline silicon for the gate material over high-K dielectrics without forming silicon dioxide on the high-K dielectric material.
High-K dielectrics are also being evaluated for memory applications as a storage capacitor cell dielectric. In some memory applications, it will also be desirable to form a polycrystalline gate over a high-K dielectric.